Superconductive computer and components therefor



Oct. 17, 1961 J. W. BREMER SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR Filed DSC. 51, 1958 l'T Sheets-Sheet 1 John IM Bremer;

H/'S Attorney Oct. 17, 1961 SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR Filed Dec. 51, 1958 J. w. BRI-:MER 3,004,705

17 Sheets-Sheet 2 PQM l Lf 50N 5a John W Bremer,

H/'s Attorney.

J. W. BREMER Oct.v 17, 1961 SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR Filed Dec. 5l, 1958 1'7 Sheets-Sheet 3 IIIIVQW A lllllvn A llllvrv A I ||Vnd ,d 5 -w M K fr m K UMMW U Pwa on L 7 ./,Nas u w w L m n l Oct. 17, 1961 J. w. BREMER 3,004,705-

SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREF'OR Filed Dec. 31. 1958 17 Sheets-Sheet 4 77115 Haft orne y Oct. 17, 1961 J. w. BRI-:MER 3,004,705

SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR Filed Deo. 5l, 1958 17 Sheets-Sheet 5 MULT/PL/ER ZI Tu/f 7715.453

mi' A 0 )LD/ PE A 0 /gjoa/a/ Inventor.- Jo/wrw l\/. Bremer;

H/'S Attorney.

Oct. 17, 1961 J. w. BREMER 3,004,705

sUPERcoNDucTIvE COMPUTER AND COMPONENTS THEREFOR Filed Dec. 51, 1958 17 Sheets-Sheet 6 T9255 -5/7 ,4e/#min U/v/r M Johr 1MB/Nemen bg H/lSAtofrweg.

J. W. BREMER Oct. 17, 1961 SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR 17 Sheets-Sheet 7 Filed Deo. 5l, 1958 Inventor.- Johrv M Brems by Maf? H/'s Attorvv J. w, BRI-:MER 3,004,705 suPEROONOUcTIvE COMPUTER AND COMPONENTS THEREFOR Oct. 1 7, 1961 17 SheeiS-Sheet 8 Filed Dec. 5l, 1958 Inventor: John Bfeme bg His Attorney.

0a. 17, 1961 J. w. BRI-:MER 3,094,705

SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR Filed Dec. 51, 1958 17 Sheet-Sheet 9 /l//S/OA/ c//ecu/rs I 7 I f5 F425/ C A-TYPE o 0 n? (305 ln /30/ vv :Mv

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FTYPE 0 cg/5 0 0 k a I /3 5 i n J\ fr f3 \l\l l l slsf" Af 'Mw/4 3x6 wf Ill Q0 l /El/ 0 mlM 0 49 vv JZ/J Ji! E Inventor:

John W Bremer,

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Oct. 17, 1961 -SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR Filed Dec. 31, 1958 17 Sheets-Sheet 10 Inventor: John W Bremer,

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J. w. BREMER 3,004,705

Oct. 17, 1961 .1.w. BREMER 3,004,705

l. SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR Filed Dec. 51, 1958 17 Sheets-Sheet 11 D/l//S/O/V 113-/ a 5 C/ 0 @ma Uil-Eg. /E 0 /7 0 c :e i l f5 #y Z 0 c y j@ 454 47j 477 Inventor:

John W Bremer,

17 Sheets-Sheet 12 7^', 4% neg- J. W. BREMER -Jo/vrw M/Breme UPPER /ls R 0mm is C" SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR (do 5t,

Oct. 17, 1961 Filed Dec. 51, 1958 DIV/SION TRUTH TABLES Oct. 17, 1961 J. W. BREMER Filed Dec. 51, 1958 SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR 17 Sheets-SheetI 15 John Wr'emer? J. W. BREMER Oct. 17, 1961 SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR lisheets-sheet 14 Filed Dec. 3l, 1958 QN h J. W. BREMER Oct. 17, 1961 SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR Filed DSC. 5l, 1958 17 Sheets-Sheet 15 Inventor: John W Bfeme by Md.

H/'S Attorney.

48 7a ERM/M44 727e ra/ 500ml/ANON fami/yr [s Il r rif# J. W. BREMER Oct. 17, 1961 SUPERCONDUCTIVE COMPUTER AND COMPONENTS THEREFOR Filed DEG. 5l, 1958 17 Sheets-Sheet 16 John W. Bremer;

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sUPERcoNDUcTIvE COMPUTER AND COMPONENTS THEREFOR Filed Dec. 5l, 1958 1'7 Sheets-Sheet 17 Inventor.- Johrv W. Bremer, by Maf/5w His Attorney- Filed Dec. 31, 1958, Ser. No. 784,285 35 Claims. (CI. 23S- 164) The present invention relates to cryogenic computers.

More specifically the invention relates to cryogenic computers, and to cryogenic arithmetic modules which can be'used in assembling a cryogenic computer.

Recently, a new innovation has been introduced into the computer eld which is known as the cryotron. The cryotron comprises a small length of superconductor, termed the gate, which is maintained below its critical temperature so that it exhibits superconductive characteristics. The gate is in turn surrounded by a winding which is likewise constructed from a superconducting material, but the material out of which the winding is formed has a higher critical magnetic field strength than the material out of which the gate is formed. As a consequence of this arrangement, electric current tlowing through the winding can be used to render the gate alternately normally resistive or superconducting in an off-on manner. Hence, a cryotron can be used as a logic element, and is particularly well suited to binary arithmetic. It is the purpose of this disclosure to describe a cryogenic computer which utilizes such cryotrons as the logic elements thereof.

It is therefore a primary object of the present invention to provide `a new and improved cryogenic computer utilizing cryotrons as logic elements.

Another object of the invention is to provide a number of different arithmetic modules fabricated from cryotrons for performing different arithmetic operations such as addition, subtraction, multiplication and division, and which may be used in constructing a cryogenic computer.

In practicing this invention a cryogenic digital arithmetic unit is provided which comprises a plurality of superconducting gate elements, there being at least two gate elements for each digit to be resolved by the unit with the pair of superconducting gate elements for one of the digits to be resolved being connected to the input end in parallel circuit relationship to a source of electric summation current, and having the remaining ends thereof connected to respective output terminals representing a binary one or a binary zero. A coil pair for the tirst digit to be resolved is arranged on the gate elements with the winding thereof representing a binary one connected to the zero output terminal. A second pair of single gate elements are connected to the first gate elements at a point intermediate the iirst digit coil pair and the output terminals, and a second digit coil pair is arranged on at least the second gate elements with the winding thereof representing a binary one surrounding the second gate element connected to the one output. The coil pairs are of course constructed from a superconducting material which has a critical magnitude field strength higher than the gate elements. In a preferred embodiment of the invention the arithmetic unit is connected to a carry unit to form an arithmetic module. The carry unit is generally similar in construction to the arithmetic unit and the binary one windings of corresponding coil pairs on the arithemtic unit and the carry unit are interconnected with the binary zero windings of corresponding coil pairs also being interconnected. In utilizing modules of the type set forth above, a plurality of such combination arithmetic and carry units are interconnected with the output of the preceding carry units being connected to a coil pair of the next succeeding carry unit which is adapted to receive the carry sum.

3,004,705 Patented Oct. 17, 1961 Other objects, features and many of the attendant advantages of this invention will be appreciated more readily as the same becomes better understood by reference to the following detailed description, when considered in connection with the accompanying drawings, wherein like parts in each of the several figures are identified by the sarne reference characters, and wherein:

FIGURE 1 is a truth table for the adder module shown in FIGURE 2;

FIGURE 2 shows the circuit details of construction of a cryogenic adder module constructed in accordance with the present invention;

FIGURE 3 is a functional block diagram showing the manner in which adder modules such as shown in FIG- URE 2 are interconnected;

FIGURE 4 is a truth table for a subtractor module shown in FIGURE 5;

FIGURE 5 shows the circuit details of construction of a cryogenic subtractor module constructed in accordance with the present invention;

FIGURE 6 is a functional block diagram showing the manner in which subtractor modules such as shown in FIGURE 5 are interconnected;

FIGURE 7 is a functional block diagram of a cryogenic multiplication network constructed in accordance with the present invention;

FIGURE 8 shows the circuit details of construction of a cryogenic beta type multipler unit employed in the multiplication network of FIGURE 7;

FIGURE 9 shows the circuit details of construction of a cryogenic gamma type multiplier module used in the multiplication network of FIGURE 7;

FIGURE 10 shows the circuit details of construction of a cryogenic alpha type multiplier module constructed in accordance with the present invention and used in the multiplication network of FIGURE 7;

FIGURE 11 shows the three truth tables for the beta type multiplier network shown in FIGURE 8, the gamma type multiplier module shown in FIGURE 9, and the alpha type multiplier module shown in FIGURE 10;

FIGURE 12 is a schematic circuit diagram of a cryogenio comparison circuit for comparing A=B, in accordance with the present invention;

FIGURE 13 shows the circuit details of construction of a comparison circuit for performing the comparison A B constructed in accordance with the present invention;

FIGURE 14 is a functional block diagram of a portion of a three-place cryogenic digital computer constructed in accordance with the present invention which performs the operation of binary addition, subtraction, comparison A=B, comparison A B, and multiplication;

FIGURE l5 shows the circuit details of construction of the addition, subtraction and two comparison stages of the cryogenic computer shown in FIGURE 14, together with the control panel therefor;

FIGURE 15a shows the circuit details of construction of the readout panel for the cryogenic computer of FIG- URE 15;

FIGURE 16 shows the circuit details of construction of the multiplication stage of the cryogenic computer` shown in FIGURE 14;

FIGURE 17 shows the circuit details of construction of a cryogenic delta divider module constructed in ac-V cord ance with the present invention;

FIGURE 18 is a circuit diagrams of a cryogenic theta divider module constructed in accordance with the present invention;

FIGURE 19 shows the circuit details of construction of a cryogenic lambda divider module constructed in accordance with the present invention;

FIGURE 20 is a circuit diagram of a cryogenic beta the teachings of the present invention;

FIGURE 23 is a schematic circuit diagram of a cyrogenie eta divider module constructed in accordance with v the present invention;

FIGURE 24 shows the truth tables for the beta, gamma, delta, epislon, eta, theta, and lambda divider modules illustrated in FIGURES 17-23;

FIGURE 25 is a functional block diagram of a division network utilizing the divider modules shown in FIGURES 17-23;

FIGURES 26-29 form the schematic circuit diagram of the division network shown in FIGURE 25 of the drawings.

One embodiment of an arithmetic module constructed in accordance with the invention is illustrated in FIGURE 2 of the drawings. In this embodiment of the invention an arithmetic module is formed from a plurality of superconducting gate elements known as cryotrons which are constructed from a suitable superconducting material. For a more complete description of the construction and operation of the cryotrons, reference is made to an article entitled Cryogenic Devices in Logical Circuitry and Storage, by I. W. Bremer, printed in the Electrical Manufacturing magazine, February 1958 issue, published by the Gage Publishing Company, and to United States Patent 2,832,897, issued April 29, 1958, Magnetically Controlled Gating Element, Dudley A. Buck, inventor. The arithmetic module illustrated in FIGURE 2 of the drawings comprises a first pair of superconducting gate elements 11 and 12 having one end thereof connected in parallel to a source of electric summation current Is supplied to the terminal 13 from any low voltage direct current electric generator. The remaining ends of the first gate elements 11 and 12 are connected to a pair of output terminals 14 and 15 representing a binary Zero and a binary one, respectively. The first gate element 11 is surrounded by a superconductivity modifying means comprising afield winding 16 that represents a binary one and first gate element 12 is surrounded by a superconductivity modifying means comprising a field winding 17 that represents a binary zero. The two superconducting field windings 16 and 17 form a iirst digit coil pair for reading a first digit to be resolved by the unit into the arithmetic module, and are fabricated from a superconducting material which has a higher critical magnetic field strength than the material out of which the gate elements 11 and 12 are fabricated in the manner described more fully in the above referenced article and patent. Because all of the arithmetic modules to be described hereinafter will utilize superconducting field windings possessing this same characteristic relative to the gate elements which they surround, it is to be undertsood that by definition, the term superconductivity modifying means, or superconductivity modifier, or superconducting field winding, means a winding or similar means possessing this characteristic. Further, the terms coil and winding mean any arrangement of superconductors whereby the gate resistance is controlled by magnetic fields produced bythe coil or winding member, and may be wound in the form of a helix, or it may be a lsingle cross wire or strip or other similar means possessing this characteristic. Connected to the first gate elements 11 and 12 are a second pair of superconducting gate elements 18 and 19 with one end of the superconducting gate element 18 being connected to the rst gate element 12 at the output side of the binary Zero winding 17 and the other end is connected to the binary one output terminal. The superconducting gate element 17 has one end connected to the first superconducting gate element 11 at the output side of the binary one winding 16 and has its remaining end connected to the binary zero output terminal. The second gate elementlS is surrounded by a superconducting field winding 21 whichrepresents a binary one, and the second gate element 19 is surrounded by a superconducting field winding 22 which represents a binary Zero. A third set of superconducting gate elements 23-26 are connected to the first two mentioned gate elements, and there are exactly double the number of gate elements in the third set of gate elements as there were in the preceding sets. The third gate elements 23 and 24 are connected to the first and second gate elements 11 and 18 `on the output side of the binary one winding with the third gate element 24 being connected to the binary one output terminal and the third gate element 23 being connected to the binary zero output terminal. Disposed about the third set of gate elements 23-26 is a coil pair comprised by a rst superconducting field winding which surrounds the two gate elements 23 and 24 and represents a binary one, and a second superconducting field winding 28 which represents a binary zero and surrounds gate elements 25 and 26. While the embodiment of the invention discloses that the superconducting field windings surround all of the preceding gate elements, plus the particular gate elements associated with any one winding, this is not an essential feature of construction of an arithmetic module constructed in accordance with the present invention for it would sufce that a coil pair surround only the particular gate elements with which it is associated. However, for convenience, the arithmetic module has been constructed in the manner disclosed.

In operation, an arithmetic module constructed in the above described manner has electric current supplied to the terminal 13 which iiows through a selected superconducting path to one of lthe output terminals representing either the binary zero or the binary one as determined by the energization of the windings of the coil pairs surrounding the various gate elements. The particular arithmetic module disclosed in FIGURE 2 comprises an adder designed to ladd together three binary digits, and to provide an output signal at the output terminal which represents the sum off the three digits. The digits to be added are supplied to the superconducting field windings of coil pairs of the lmodule with the coil pair formed by windings 16 and 17 representing a carry sum to be added, the coil pair formed by the windings 21 and 22 representing a second sum which shall be identified as Bn, and the coil pair 27 and Z8 representing a third sum which shall be identified `as An. The truth table for the arithmetic module illustrated in FIGURE 2. of the drawings is shown in FIGURE 1 of the drawings wherein it can be seen that if An represents the addend, Bn the augend, Sn shall be the sum, Cn 1 shall be the carry sum supplied to the coil pair 16 and 17. In using the truth table of FIGURE 1 the value An to be `added is listed in the two vertical columns to the right of the character An. The value Bn to be added is listed in the single Vertical column below the character Bn, and the values for Cn 1 are lis-ted in the four vertical columns to t-he left of the identification character Cn 1. This truth table was worked out by actually -adding the binary numerals illustrated An and Bn and C 1 to be added, and provide the answer for all of the possible combinations of values for An, B,l1 and Cn 1. For an example in the use of the truth table, assume that it is desired to determine the sum of An=0, Bn=1, and Cn 1=l. It is necessary to select the An=0 column, the Bn=1 line and C 1=1 column in the output sum heading identified by the numeral Sn. By reading down the An=0 and Cn 1=l column, and lacross the Bn=l line, it is seen that the output sum is equal to zero. Similar readings can be made for any other combination of the three factors An, I3,1 'and Cn 1. The following lis-ted figures shows the output sum as WGll aS-the carry'sum, to bedis` cussed hereinafter, obtained from the output of the arithmetic unit for each of the eight various combinations of values that are possible with the three stage arithmetic unit illustra-tedin FIGURE 2.

s.. A.. B.. 0..-1 C..

o o ov o o 1 o o 1 o 3 i i i 1 s o o o 10 o 1 o 1 1 o 1 1 o 1 1 1 1 1 1 In tracing thro-ugh the operation of the arithemetic unit shown in FIGURE 2, from an examination of the above table, the operation of the `arithmetic module shown in FIGURE 2 will become apparent. For eX- ample, assume that An=0, Bn=l and Cn 1=0. It can be seen that the output sum will equal one from the above table and the truth table shown in FIGURE l. From a simple yarithmetic process it is also `apparent that this is the answer. In tracing through the operation of the arithmetic module now, assume that for the values of An, Bn and C 1 selected, that electric current will ow through the binary zero winding 17 representing An=0, through the binary one winding 21 representing Bn=1, and through the binary zero winding 28 representing C 1=0. Electric current flow through each of the windings 17, 21 and 28 causes 4an electromagnetic field to build up which cuts the gate elements which these windings surround and results in raising the resistivity of the gate elements above Ithe superconducting state. Accordingly, the gate elements surrounded by these windings will exhibit a normal conductivity, and hence will 5 possess some resistivity, while the superconducting gate elements which are not surrounded by such `an electromagnetic eld will continue to be superconducting, and in effect will exhibit zero resistivity. As la consequence, it is possible to trace out one superconducting path extending between the source of summation current ls and either one of lthe two output terminals. In the specific example in mind, this path will constitute the part of superconducting gate element ill surrounded by the binary one winding '16 of the Cn 1 numeral coil pair since this winding is unenergized, the part of superconducting gate element 19 surrounded by the binary zero winding 22 of the Bn numeral coil pair, and supenconducting gate element 23 which is surrounded by the binary one winding of the An numeral coil pair. It can be appreciated that t'his superconducing path is connected to the one output terminal, and hence, the answer shown by the truth table to be the correct answer is obtained through the operation of arithmetic module. For all other eight combinations of input factors set forth in the preceding table, one such superconducting path will result providing ythe correct answer at the output terminals of the arithmetic module.

From examination of the above table, it can be appreciated that for certain combinations of numerals there will be a carry sum due to the nature of binary addition. These carry sums Iare listed to the right of the above table. For example An=l plus Bn=1 provides an output sum of zero, but a carry sum of one. In order to develp these carry sums and supply them to the next succeeding stage in an addition operation being carried out, a carry unit is provided. A carry unit for the arithmetic unit shown in FIGURE 2 is `illustrated just below the arithmetic unit.

To all intents and purposes the carry unit is identical in construction to the arithmetic unit with the exception that certain of the gate elements are connected to different output terminals representing either a binary zero or a binary one. For example, in the carry unit the superconducting gate element 1'8 of the carry unit is connected to the binary zero output termin-al as opposed to its correspending gate element 18 in the arithmetic unit which is connected to the binary one output terminal, and the gate element 19 is connected to the one output terminal as opposed to its corresponding gate element 19 inthe arithmetic unit which is connected to the zero output terminal. Other structural differences include the superconducting gate element 23 which is connected to the zero output terminal, the gate element 24 connected to the one output terminal, the gate element 2-5 is connected to the one output terminal, and the gate element 26 is connected to the binary zero output terminal. The coil pairs for the different digits to be resolved are connected surrounding the corresponding superconducting gate elements, and are similar in construction to the coil pairs formed on the adder unit. In fact, the coil pairs on the carry unit lare connected directly to each of the coil pairs on the arithmetic module for convenience, and to assure that the carry unit is supplied with the same problem as supplied to the arithmetic module. Accordingly, the binary zero windings 17 and 17 for the (2 1 digit are interconnected, as are the binary one windings 16 and 16', and similarly for each of the other two digits An and Bn to be resolved by the module. From an examination of the truth table shown in FIGURE 1, the carry sum obtained at the output terminals of the carry unit can be derived. For example, assuming An=l, Bn=1 and Cn 1=l, the answer will be one for the output signal Cn for the carry unit. Now examining the carry unit it can be seen that for the example cited, current will ow in the binary one winding 116 of the Cn 1 digit, the binary one winding 21 of the VB,J digit, and the binary one winding 27 of the A,1 digit. Accordingly, one of the conductors which is not surrounded by each of these three windings will provide the superconducting path between the source of summation current I,z and the output terminals. Only the superconducting gate element 12 will provide such a superconducting path, and it is connected to the one output terminal. Similar combination of inputs listed in the above table wil-l provide only one superconducting path between the input side of the carry unit and the output terminals so that output current is provided selectively at either the binary one or the binary zero ou-tput terminal of the unit.

In utilizing the arithmetic module with other such modules to perform an arithmetic network, the modules are interconnected in the manner shown in the schematic block diagram of FIGURE 3. In this arrangement, the first set of digits to be resolved A0 and B0 are supplied to the secon-d and third coil pairs in the adder unit and the first digit coil pair has the Cn 1 or I carry current supplied with the summation current Is being supplied to the iirst unit. This first unit will then perform the binary addition operation with respect to A0, B0 and 10am., and provide at its two output terminals 'the carry output current and a sum output current. A part of the sum output current may be connected to the next successive stage as a source of summation current 'Is together with the carry sum C 1=C0. This next stage will then perform the binary addition of A1, B1 and C0, and so on down the `line until A2, B2 and C1, and An, Bn and C1 are added to provide at the output terminals output signals respresentative of the sums S0, S1, S2, and Sn resulting from the four diierent binary addition operations. The manner in which these modules are interconnected in a computer to form a more involved addition network will be described more fully hereinafter with respect to the embodiment ofthe invention disclosed in block diagram form in FIGURE 22 of the drawings.

An arithmetic module for use as a subtractor is illustrated in FIGURE 5 of the drawings. This subtractor module comprises a first pair of superconducting gate elements 315 `'and 36 connected in parallel circuit relationship to a source of summation current Is, with the superconducting gate element 315 being connected directly to the zero output terminal, and the superconducting gate element 36 being connected directly to the binary one output 

